From d96fdbf04cece60b8c88d94b08095acafb0a2b27 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:27 +0300 Subject: [PATCH 0917/1625] drm/i915: pass dev_priv explicitly to BCLRPAT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the BCLRPAT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/f04d0313032d5820a14cc504af390b4b1006fae6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crt.c | 10 ++++++---- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 15569cf96c9c..2660c4a53e6f 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -193,7 +193,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, adpa |= ADPA_PIPE_SEL(crtc->pipe); if (!HAS_PCH_SPLIT(dev_priv)) - intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); + intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0); switch (mode) { case DRM_MODE_DPMS_ON: @@ -707,7 +707,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); - save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); + save_bclrpat = intel_de_read(dev_priv, + BCLRPAT(dev_priv, cpu_transcoder)); save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)); vblank = intel_de_read(dev_priv, @@ -720,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; /* Set the border color to purple. */ - intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050); + intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050); if (DISPLAY_VER(dev_priv) != 2) { u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); @@ -800,7 +801,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) } /* Restore previous settings */ - intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat); + intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), + save_bclrpat); return status; } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 776e4450e4af..49f7ac0f7997 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1870,7 +1870,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) /* Border color in case we don't scale up to the full screen. Black by * default, change to something else for debugging. */ - intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); + intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0); } /* Prefer intel_encoder_is_combo() */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f87fb2d015e..39f92739b822 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1142,7 +1142,7 @@ #define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) #define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) #define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) -#define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) +#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) #define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) #define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) -- 2.52.0